Nonvolatile (nV) memory, such as flash memory, has traditionally had a small, fixed initialization delay after power is applied or a reset operation is performed before a read operation could be carried out. Because the delay was small and predictable, it was usually tolerable within a digital system. Newer nV memory technologies, on the other hand, may include additional functionality that can increase post reset initialization delays and make them indeterminate. For example, features such as embedded security, power loss recovery, and/or others within nV memories can result in post reset delays that are not as predictable as delays in memories of the past. Techniques and structures are needed for dealing with such indeterminate delays.